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Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level
A leading technology company based in Australia is seeking a qualified candidate with at least 5 years of experience to manage synthesis and STA flows, develop scripts for design closure activities, and interact with various teams
Role Hands on ownership of Synthesis / Constraints / STA / ECO flow. Expert in running Block level and Chip level STA in MCMM, DMSA environments. Must have worked on multiple timing closure and constraint development