Role Hands on ownership of Synthesis / Constraints / STA / ECO flow. Expert in running Block level and Chip level STA in MCMM, DMSA environments. Must have worked on multiple timing closure and constraint development for
Overview We are looking for a passionate and talented Verification Engineer to join a cutting-edge SoC design team in Adelaide. Youll work on complex digital and mixed-signal systems that power innovative technologies across multiple industries. If